1. Field of the Invention
The invention relates to a semiconductor integrated circuit and a memory module, and particularly relates to a structure for equalizing lengths of interconnections of a plurality of data I/O (input/output) pins.
2. Description of the Background Art
In recent years, capacities of main memories of servers, work stations, personal computers and others have been increased, and consequently, there are increasing tendencies to increase capacities of memory modules (DIMMs: dual inline memory modules) forming the main memories.
The capacity of memory module can be increased, e.g., by increasing the memory capacities of Dynamic Random Access Memories (DRAMs) carried on the module, reducing a size of a package of each chip and thereby increasing the number of on-board chips, or employing a stack module structure.
Among the above, employment of the stack module is not technologically easy, and requires a high assembling cost. Further, it is expensive to increase the memory capacity of the on-board dynamic random access memory DRAM.
For the above reason, such a memory module has been developed that uses a conventional DRAM employing an inexpensive Thin Small Outline Package (TSOP) or an inexpensive Small Outline J-leaded package (SOJ) for increasing the number of on-board memory chips of the memory module.
The conventional memory module will now be described with reference to FIG. 20. The memory module shown in FIG. 20 includes a module substrate 90, a plurality of memory chips 91A-91F arranged on module substrate 90 and a connect pin group 92 arranged on one side of module substrate 90. Each of the plurality of memory chips 91A-91F is accommodated in a thin small outline package (TSOP). Each memory chip has a plurality of data I/O pins for transferring write data to be written into the memory cell array and read data read from the memory cell array. The plurality of data I/O pins are arranged on the opposite ends of the package (QX and QY). A 1st pin Q1 and a 1st pin Qi on the opposite side are provided for power supply.
The plurality of memory chips 91A-91C and the plurality of memory chips 91D-91F are arranged in two rows. Data is transmitted between a memory controller (not shown) and connect pin group 92. The memory chips operate in accordance with signals sent through connect pin group 92. Data I/O pin groups QX and QY of each of memory chips 91A-91F receive the write data from data I/O pin group included in connect pin group 92, and send the read data to the data I/O pin group included in connect pin group 92.
However, the conventional memory module suffers from such a problem that interconnections connecting the respective memory chips to connect pin group 92 have various lengths (interconnection lengths). For example, data I/O pin group QX of memory chip 91A and data I/O pin group QY of memory chip 91D are spaced from connect pin group 92 by different distances, respectively. Therefore, a data transfer time between memory chip 91D and the memory controller is longer than that between the memory chip 91A and the memory controller.
For eliminating the difference in data transfer time, the memory chips may be reduced in number. However, this cannot satisfy the demand for increased capacities.
For example, the interconnections between the memory chip 91A and the connect pin group 92 may be arranged in a folded fashion so that the interconnection length between data I/O pin group QX of memory chip 91A and connect pin group 92 may be equal to that between data I/O pin group QY of memory chip 91D and connect pin group 92. However, arrangement of such complicated interconnection patterns is difficult. Further, increase in interconnection length lowers the operation performance of memory chip 91A.
The above problem arises in connection with not only the data I/O pins but also signal pins in connect pin group 92 controlling internal operations of the memory chip.
According to JEDEC (Joint Electron Device Engineering Council) standards, it is specified as the standard to be satisfied that the data I/O pins and the predetermined signal pins in each memory chip must be connected to the connect pin group via interconnections of lengths equal to those for the other memory chips.
Accordingly, the invention provides a semiconductor integrated circuit, in which interconnections of equal lengths can be easily employed for predetermined pins when used in a memory module.
According to an aspect of the invention, a semiconductor integrated circuit includes a memory cell array including a plurality of memory cells arranged in rows and columns, an internal circuit for writing data into the memory cell array or reading data from the memory cell array, and a package including a plurality of pins and surrounding the memory cell array and the internal circuit. The plurality of pins are arranged on at least two surfaces forming the package. The plurality of pins include a plurality of data I/O pins for externally receiving the data to be written into the memory cell array and externally sending the data read from the memory cell array. All the plurality of data I/O pins are arranged at least one of the two surfaces.
Preferably, the plurality of pins further include a plurality of signal pins disposed on a surface opposed to the surface carrying all the plurality of data I/O pins for externally transmitting signals with respect to the internal circuit.
Preferably, the package is a thin small outline package (TSOP).
Preferably, the plurality of pins further include a control pin receiving a signal controlling a predetermined operation of the internal circuit, and the control pin is arranged on the surface carrying all the plurality of data I/O pins. Particularly, the package transmits signals to and from a plurality of connect pins arranged on a module substrate carrying the package, and the control pin is directly connected to a specific connect pin among the plurality of connect pins.
According to the semiconductor integrated circuit described above, since the data I/O pins are gathered on the one surface of the package, lengths of interconnections to the data I/O pins can be easily equalized in the memory module employing a plurality of circuits each formed of the above semiconductor integrated circuit.
An inexpensive thin small outline package (TSOP) may be used.
The specific pin and the data I/O pin may be arranged on the same surface so that lengths of interconnections to the specific pins can be easily equalized in the memory module employing a plurality of circuits each formed of the above semiconductor integrated circuit.
According to another aspect of the invention, a semiconductor integrated circuit includes a memory cell array including a plurality of memory cells arranged in rows and columns, an internal circuit for writing data into the memory cell array or reading data from the memory cell array, and a package including a plurality of data I/O pins for externally receiving the data to be written into the memory cell array and externally sending the data read from the memory cell array, and surrounding the memory cell array and the internal circuit, all the plurality of data I/O pins being arranged near one side forming an outer periphery of a predetermined surface of the package. Preferably, the package is a chip scale package (CSP), and all the plurality of data I/O pins are arranged on the same line.
According to the semiconductor integrated circuit described above, since the data I/O pins are gathered near one side forming the outer periphery of the one surface of the package, lengths of interconnections to the data I/O pins can be easily equalized in the memory module employing a plurality of circuits each formed of the above semiconductor integrated circuit. In particular, the chip scale package which is inexpensive can be used.
Still another object of the invention is to provide a memory module which can perform efficient data transmission without lowering an operation performance of a memory chip.
According to still another aspect of the invention, a memory module includes a connect pin group including a plurality of connect pins for externally transmitting signals, a plurality of memory chips operated by transmission of the signals with respect to the connect pin group, and a module substrate provided with the connect pin group, each of the plurality of memory chips having a memory cell array including a plurality of memory cells arranged in rows and columns, an internal circuit for writing data into the memory cell array or reading data from the memory cell array, and a package having a plurality of data I/O pins for externally receiving the data to be written into the memory cell array and externally sending the data read from the memory cell array, and surrounding the memory cell array and the internal circuit, all the plurality of data I/O pins being arranged on a predetermined surface of the package or in a portion neighboring to the predetermined surface and located in a surface in contact with the predetermined surface, the plurality of memory chips being divided into first and second chip rows for arrangement, and the plurality of memory chips being arranged such that each of the predetermined surfaces in the first row is opposed to the predetermined surface in the second chip row.
Preferably, the first and second chip rows are parallel to the connect pin group.
Preferably, the package is a thin small outline package TSOP, and all the plurality of data I/O pins are arranged on the predetermined surface.
Preferably, the package further includes a control pin arranged on the predetermined surface for receiving a signal controlling a predetermined operation of the internal circuit, and the control pin is directly connected to a specific connect pin among the plurality of connect pins.
Preferably, the package is a chip scale package CSP, and all the plurality of data I/O pins are arranged on the same line neighboring to the predetermined surface and located in the surface in contact with the predetermined surface.
Preferably, the plurality of data I/O pins are divided for arrangement in the portion neighboring to the predetermined surface and located in a first surface in contact with the predetermined surface and arrangement in the portion neighboring to the predetermined surface and located in a second surface in contact with the predetermined surface.
According to the memory module described above, the connect pins in the memory module and the data I/O pins of the respective memory chips can be arranged to employ interconnections of substantially equal lengths between them. Thereby, the data transmission can be performed efficiently without lowering the operation performance of the respective memory chips. Further, the JEDEC standards can be satisfied.
An inexpensive thin small outline package TSOP or an inexpensive chip scale package CSP may be used.
For specific pins, distances to the connect pin group can be substantially equal to each other. Thereby, a fast operation can be ensured.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.